The present invention relates to programmable routing structures that provide fast paths for input/output signals, and more particularly, to a programmable routing structures that reduce delay for signals driven to and from input/outputs pads of an integrated circuit.
Programmable logic integrated circuits (ICs) can be configured to perform a variety of user functions. Programmable logic ICs include programmable logic devices (PLDs), field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), etc. Programmable logic ICs typically have numerous logic blocks (also called logic elements) that can be configured to implement various combinatorial and sequential functions.
The logic blocks have access to a programmable interconnect structure. The programmable interconnect structure can be programmed to interconnect the logic blocks in almost any desired configuration. Logic blocks are often grouped into logic array blocks or macrocells. Programmable logic ICs typically include numerous input and output pads on the die.
A complex programmable logic device (CPLD) is a type of PLD that usually contains non-volatile memory. The MAX 7000 manufactured by Altera Corporation of San Jose, Calif. is an example of a CPLD that contains on-chip non-volatile memory. The MAX 7000 includes a global routing network of vertical interconnects. Each input/output (I/O) pad on the MAX 7000 is connected to the global routing network.
In the MAX 7000, every output signal that is transmitted to an output pad from a macrocell is routed through the global routing network. Every input signal that is received at an input pad is routed to the global routing network before being routed to a macrocell. The global routing network in the MAX 7000 is also used to route signals from one macrocell to another macrocell. Thus, all signals that are transmitted between macrocells and I/O pads are routed through the global routing network.
The MAX 7000 architecture provides roughly the same delay time to transmit a signal from one macrocell to another and between I/O pads and a macrocell. As applications for PLDs have become more complex, customers have continue to demand more logic blocks on each PLD die. However, signal delay times increase by a factor of 4 each time the amount of logic on a chip containing the MAX 7000 architecture is increased by a factor of 2.
CPLDs such as the MAX 7000 typically require short delay times for signals that are routed from pad-to-pad and between pads and registers. Therefore, a need has developed for a routing network on a chip that provides short signal delay times for signals transmitted to and from input and output pads.